Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems
نویسندگان
چکیده
منابع مشابه
A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor
In Chip multiprocessor (CMP) systems, DRAM memory is a critical resource shared among cores. Scheduled by one single memory controller, memory access requests from different cores may interfere with each other. This interference causes extra waiting time for threads and leads to negligible overall system performance loss. In conventional thread-unaware memory scheduling patterns, different thre...
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ژورنال
عنوان ژورنال: Transactions of the Institute of Measurement and Control
سال: 2017
ISSN: 0142-3312,1477-0369
DOI: 10.1177/0142331217715064